Electronic devices may be formed on thin-film silicon-on-insulator (SOI) substrates with reduced short channel effects, reduced parasitic and nodal capacitances, increased radiation hardness, reduced susceptibility to parasitic thyristor latch-up and reduced process complexity compared to bulk semiconductor devices. In addition, fully depleted SOI devices (e.g., FETs) may offer reduced short channel effects (SCE), near ideal sub-threshold slope, increased transconductance and reduced threshold voltage sensitivity to changes in body doping, channel length, temperature and substrate voltage. The "kink" effect and threshold voltage shifts caused by body charging are also significantly reduced in fully depleted SOI devices.
But conventional SOI devices have a "floating body" in which the body or channel region of the device (e.g., FET) is located on an insulator and is not electrically connected to a fixed potential. Devices susceptible to floating body effects (FBE) can experience high leakage current and parasitic bipolar action. As will be understood by those skilled in the art, these limitations can be reduced by providing a contact to the body so that a fixed potential can be applied thereto. Unfortunately, the use of body contacts typically increases the size of SOI devices. Attempts have also been made to limit FBE by providing non-uniformly doped channel regions, however, the use of non-uniformly doped channel regions may cause a shift in a device's threshold voltage.
One attempt to form an SOI MOSFET according to the prior art is disclosed in FIGS. 1-4. In particular, FIG. 1 illustrates an SOI MOSFET comprising an insulating layer 12 on a semiconductor substrate 10 and a plurality of field oxide isolation regions 14 on the insulating layer 12. An active region extending between adjacent field oxide isolation regions 14 comprises source, channel and drain regions 18, 20 and 16, respectively. An insulated gate electrode is also provided on the channel region 20. The insulated gate electrode comprises a gate oxide layer 22 and a gate electrode 23. A passivation layer 26 is also provided on the field oxide isolation regions 14 and insulated gate electrode. Contact holes 28 are provided in the passivation layer 26 and source and drain contacts 30 are provided in the contact holes 28.
Referring now to FIGS. 2-4, a method of forming the SOI MOSFET of FIG. 1 will be described. In particular, FIG. 2 illustrates the steps of forming an insulating layer 12 on a face of a semiconductor substrate 10 and then forming a semiconductor layer 13 (e.g., N-type or P-type silicon) on the insulating layer 12. Then, a plurality of field oxide isolation regions 14 are provided in the semiconductor layer 13 to define semiconductor active regions extending therebetween. An insulated gate electrode 24, comprising a gate oxide layer 22 and a gate electrode 23, is then formed on an active region using conventional techniques. Source and drain region dopants of predetermined conductivity type are then implanted into the active region (using the insulated gate electrode as an implant mask) to define self-aligned source and drain regions 18 and 16, respectively. As will be understood by those skilled in the art, the edges of the source and drain regions define a channel region 20 therebetween. Here, for example, the semiconductor layer 13 may be of P-type conductivity and the source and drain region dopants may be of N-type conductivity. Referring now to FIG. 4, a passivation layer 26 (e.g., BPSG) is then formed on the intermediate structure of FIG. 3. Contact holes 28 are then patterned in the passivation layer 26 using conventional techniques, to expose the source and drain regions 18 and 16. A layer of metallization is then deposited into the contact holes 28 and patterned to define source and drain electrodes 30.
As illustrated, the SOI MOSFET of FIGS. 1 and 4 is isolated from adjacent devices by the field oxide isolation regions 14 and the insulating layer 12. Unfortunately, such isolation typically causes floating body effects (FBE) which may include the accumulation of holes in the channel region 20 in the event the MOSFET is an NMOS device. As will be understood by those skilled in the art, such floating body effects can cause threshold voltage shift and adversely effect the I-V characteristics of the MOSFET.
Thus, notwithstanding prior art attempts to form SOI substrates and devices, there still continues to be a need for improved methods of forming SOI substrates and devices so that devices formed therein derive the above described benefits of SOI isolation, but do not suffer from excessive floating body and short channel effects.